1 data sheet acquired from harris semiconductor schs202c features fully static operation buffered inputs common reset negative edge clocking fanout (over temperature range) - standard outputs . . . . . . . . . . . . . . . 10 lsttl loads - bus driver outputs . . . . . . . . . . . . . 15 lsttl loads wide operating temperature range . . . -55 o c to 125 o c balanced propagation delay and transition times signi?ant power reduction compared to lsttl logic ics hc types - 2v to 6v operation - high noise immunity: n il = 30%, n ih = 30% of v cc at v cc = 5v hct types - 4.5v to 5.5v operation - direct lsttl input logic compatibility, v il = 0.8v (max), v ih = 2v (min) - cmos input compatibility, i l 1 a at v ol , v oh description the ?c4024 and ?ct4024 are 7-stage ripple-carry binary counters. all counter stages are master-slave ?p-?ps. the state of the stage advances one count on the negative transition of each input pulse; a high voltage level on the mr line resets all counters to their zero state. all inputs and outputs are buffered. pinout cd54hc4024, cd54hct4024 (cerdip) CD74HC4024 (pdip, soic, tssop) cd74hct4024 (pdip, soic) top view ordering information part number temp. range ( o c) package cd54hc4024f3a -55 to 125 14 ld cerdip cd54hct4024f3a -55 to 125 14 ld cerdip CD74HC4024e -55 to 125 14 ld pdip CD74HC4024m -55 to 125 14 ld soic CD74HC4024mt -55 to 125 14 ld soic CD74HC4024m96 -55 to 125 14 ld soic CD74HC4024pw -55 to 125 14 ld tssop CD74HC4024pwr -55 to 125 14 ld tssop CD74HC4024pwt -55 to 125 14 ld tssop cd74hct4024e -55 to 125 14 ld pdip cd74hct4024m -55 to 125 14 ld soic note: when ordering, use the entire part number. the suf?es 96 and r denote tape and reel. the suf? t denotes a small-quantity reel of 250. cp mr q 7 q 6 q 5 q 4 gnd v cc nc q 1 q 2 nc q 3 nc 1 2 3 4 5 6 7 14 13 12 11 10 9 8 november 1997 - revised october 2003 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright 2003, texas instruments incorporated cd54hc4024, CD74HC4024, cd54hct4024, cd74hct4024 high-speed cmos logic 7-stage binary ripple counter [ /title ( cd74 h c402 4 , c d74 h ct40 2 4) / sub- j ect ( high s peed c mos
2 functional diagram logic diagram 12 11 9 5 3 4 6 1 2 mr q 7 q 6 q 5 q 4 q 3 q 2 q 1 cp truth table cp count mr output state l no change l advance to next state x h all outputs are low h = high voltage level, l = low voltage level, x = don? care, = transition from low to high level, = transition from high to low. 12 q 1 cp q cp q 1 r cp q cp q 2 r 11 q 2 cp q cp q 3 r 9 q 3 cp q cp q 4 r 6 q 4 cp q cp q 5 r 5 q 5 cp q cp q 6 r 4 q 6 cp q cp q 7 r 3 q 7 cp mr 2 1 gnd v cc 7 14 q1 cd54hc4024, CD74HC4024, cd54hct4024, cd74hct4024
3 absolute maximum ratings thermal information dc supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 7v dc input diode current, i ik for v i < -0.5v or v i > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . 20ma dc output diode current, i ok for v o < -0.5v or v o > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 20ma dc output source or sink current per output pin, i o for v o > -0.5v or v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 25ma dc v cc or ground current, i cc . . . . . . . . . . . . . . . . . . . . . . . . . 50ma operating conditions temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c supply voltage range, v cc hc types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2v to 6v hct types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5v to 5.5v dc input or output voltage, v i , v o . . . . . . . . . . . . . . . . . 0v to v cc input rise and fall time 2v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (max) 4.5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (max) 6v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (max) thermal resistance (typical, note 1) ja ( o c/w) e (pdip) package . . . . . . . . . . . . . . . . . . . . . . . . . 80 m (soic) package . . . . . . . . . . . . . . . . . . . . . . . . 86 pw (tssop) package. . . . . . . . . . . . . . . . . . . . . . 113 (maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not im plied. note: 1. the package thermal impedance is calculated in accordance with jesd 51-7. dc electrical speci?ations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hc types high level input voltage v ih - - 2 1.5 - - 1.5 - 1.5 - v 4.5 3.15 - - 3.15 - 3.15 - v 6 4.2 - - 4.2 - 4.2 - v low level input voltage v il - - 2 - - 0.5 - 0.5 - 0.5 v 4.5 - - 1.35 - 1.35 - 1.35 v 6 - - 1.8 - 1.8 - 1.8 v high level output voltage cmos loads v oh v ih or v il -0.02 2 1.9 - - 1.9 - 1.9 - v -0.02 4.5 4.4 - - 4.4 - 4.4 - v -0.02 6 5.9 - - 5.9 - 5.9 - v high level output voltage ttl loads - - --- - - - - v -4 4.5 3.98 - - 3.84 - 3.7 - v -5.2 6 5.48 - - 5.34 - 5.2 - v low level output voltage cmos loads v ol v ih or v il 0.02 2 - - 0.1 - 0.1 - 0.1 v 0.02 4.5 - - 0.1 - 0.1 - 0.1 v 0.02 6 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads - - --- - - - - v 4 4.5 - - 0.26 - 0.33 - 0.4 v 5.2 6 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc or gnd -6-- 0.1 - 1- 1 a quiescent device current i cc v cc or gnd 0 6 - - 8 - 80 - 160 a cd54hc4024, CD74HC4024, cd54hct4024, cd74hct4024
4 hct types high level input voltage v ih - - 4.5 to 5.5 2- - 2 - 2 - v low level input voltage v il - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 v high level output voltage cmos loads v oh v ih or v il -0.02 4.5 4.4 - - 4.4 - 4.4 - v high level output voltage ttl loads -4 4.5 3.98 - - 3.84 - 3.7 - v low level output voltage cmos loads v ol v ih or v il 0.02 4.5 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads 4 4.5 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc and gnd 0 5.5 - - 0.1 - 1- 1 a quiescent device current i cc v cc or gnd 0 5.5 - - 8 - 80 - 160 a additional quiescent device current per input pin: 1 unit load ? i cc (note 2) v cc -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 a note: 2. for dual-supply systems theoretical worst case (v i = 2.4v, v cc = 5.5v) specification is 1.8ma. dc electrical speci?ations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hct input loading table input unit loads cp, mr 0.5 note: unit load is ? i cc limit speci?d in dc electrical table, e.g., 360 a max at 25 o c. prerequisite for switching speci?ations parameter symbol v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min max min max min max hc types maximum input pulse frequency f max 2 6 - 5 - 4 - mhz 4.5 30 - 24 - 20 - mhz 6 35 - 29 - 24 - mhz input pulse width t w 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns reset removal time t rem 2 50 - 65 - 75 - ns 4.5 10 - 13 - 15 - ns 6 9 - 11 - 13 - ns cd54hc4024, CD74HC4024, cd54hct4024, cd74hct4024
5 reset pulse width t w 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns hct types maximum input pulse frequency f max 4.5 25 - 20 - 16 - mhz input pulse width t w 4.5 20 - 25 - 30 - ns reset recovery time t rec 4.5 10 - 13 - 15 - ns reset pulse width t w 4.5 20 - 25 - 30 - ns switching speci?ations input t r , t f = 6ns parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max hc types propagation delay time (figure 1) t plh, t phl c l = 50pf 2 - - 140 - 175 - 210 ns cp to q1?output 4.5 - - 28 - 35 - 42 ns c l =15pf 5 - 11 - - - - - ns c l = 50pf 6 - - 24 - 30 - 36 ns q n to q n + 1 t plh, t phl c l = 50pf 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns c l =15pf 5 - 6 - - - - - ns c l = 50pf 6 - - 13 - 13 - 19 ns mr to q n t plh, t phl c l = 50pf 2 - - 170 - 215 - 255 ns 4.5 - - 34 - 43 - 51 ns 5 - 14 - - - - - ns 6 - - 29 - 27 - 43 ns output transition time (figure 1) t tlh ,t thl c l = 50pf 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns input capacitance c in c l = 50pf - - - 10 - 10 - 10 pf power dissipation capacitance (notes 3, 4) c pd c l =15pf 5 - 30 - - - - - pf hct types propagation delay time (figure 2) t plh, t phl c l = 50pf 4.5 - - 40 - 50 - 60 ns cp to q1?output c l =15pf 5 - 17 - - - - - ns q n to q n + 1 t plh, t phl c l = 50pf 4.5 - - 15 - 19 - 22 ns c l =15pf 5 - 6 - - - - - ns mr to q n t plh, t phl c l = 50pf 4.5 - - 40 - 50 - 60 ns c l =15pf 5 - 17 - - - - - ns prerequisite for switching speci?ations (continued) parameter symbol v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min max min max min max cd54hc4024, CD74HC4024, cd54hct4024, cd74hct4024
6 output transition t tlh ,t thl c l = 50pf 4.5 - - 15 - 19 - 22 ns input capacitance c in c l =15pf - - - 10 - 10 - 10 pf power dissipation capacitance (notes 3, 4) c pd c l =15pf 5 - 30 - - - - - pf notes: 3. c pd is used to determine the dynamic power consumption, per package. 4. p d =v cc 2 f i + (c l v cc 2 fi/m) where: m = 2 1 ,2 2 ,2 3 ,2 4 ,2 5 ,2 6 ,2 7 f i = input frequency, c l = output load capacitance, v cc = supply voltage. switching speci?ations input t r , t f = 6ns (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max test circuits and waveforms note: outputs should be switching from 10% v cc to 90% v cc in accordance with device truth table. for f max , input duty cycle = 50%. figure 1. hc clock pulse rise and fall times and pulse width note: outputs should be switching from 10% v cc to 90% v cc in accordance with device truth table. for f max , input duty cycle = 50%. figure 2. hct clock pulse rise and fall times and pulse width figure 3. hc and hcu transition times and propaga- tion delay times, combination logic figure 4. hct transition times and propagation delay times, combination logic clock 90% 50% 10% gnd v cc t r c l t f c l 50% 50% t wl t wh 10% t wl + t wh = fc l i clock 2.7v 1.3v 0.3v gnd 3v t r c l = 6ns t f c l = 6ns 1.3v 1.3v t wl t wh 0.3v t wl + t wh = fc l i t phl t plh t thl t tlh 90% 50% 10% 50% 10% inverting output input gnd v cc t r = 6ns t f = 6ns 90% t phl t plh t thl t tlh 2.7v 1.3v 0.3v 1.3v 10% inverting output input gnd 3v t r = 6ns t f = 6ns 90% cd54/74hc4024, cd54/74hct4024
mechanical data mtss001c january 1995 revised february 1999 post office box 655303 ? dallas, texas 75265 pw (r-pdso-g**) plastic small-outline package 14 pins shown 0,65 m 0,10 0,10 0,25 0,50 0,75 0,15 nom gage plane 28 9,80 9,60 24 7,90 7,70 20 16 6,60 6,40 4040064/f 01/97 0,30 6,60 6,20 8 0,19 4,30 4,50 7 0,15 14 a 1 1,20 max 14 5,10 4,90 8 3,10 2,90 a max a min dim pins ** 0,05 4,90 5,10 seating plane 0 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153
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